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EL7104
Data Sheet July 6, 2006 FN7113.2
High Speed, Single Channel, Power MOSFET Driver
The EL7104 is a matched driver IC that improves the operation of the industry-standard TC-4420/29 clock drivers. The Elantec version is a very high speed driver capable of delivering peak currents of 1A into highly capacitive loads. The high speed performance is achieved by means of a proprietary "Turbo-Driver" circuit that speeds up input stages by tapping the wider voltage swing at the output. Improved speed and drive capability are enhanced by matched rise and fall delay times. These matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and clock skew problems. This improved performance is accompanied by a 10-fold reduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with CMOS drivers. The EL7104 is available in 8-pin SO and 8-pin PDIP packages and is specified for operation over the full -40C to +85C temperature range.
Features
* Industry-standard driver replacement * Improved response times * Matched rise and fall times * Reduced clock skew * Low output impedance * Low input capacitance * High noise immunity * Improved clocking rate * Low supply current * Wide operating range * Separate drain connections * Pb-Free available (RoHS compliant)
Applications
* Clock/line drivers * CCD drivers * Ultrasound transducer drivers * Power MOSFET drivers * Switch mode power supplies * Resonant charging * Cascoded drivers
Ordering Information
PART NUMBER EL7104CN EL7104CNZ EL7104CS EL7104CS-T7 EL7104CS-T13 EL7104CSZ (See Note) EL7104CSZ-T7 (See Note) PART MARKING EL7104CN TAPE & PACKAGE REEL 8 Ld PDIP 7" 13" 7" 13" PKG. DWG. # MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
EL7104CN Z 8 Ld PDIP* 7104CS 7104CS 7104CS 7104CSZ 7104CSZ 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free)
Pinout
EL7104 (8-PIN SO, PDIP) TOP VIEW
V+ 1 IN 2 NC 3 GND 4 8 V+ 7 P_OUT 6 N_OUT 5 GND
EL7104CSZ-T13 7104CSZ (See Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7104
Absolute Maximum Ratings (TA = 25C)
Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4A Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL VHVS OUTPUT ROH ROL IOUT IPK IDC Pull-Up Resistance
V+ = 15V, TA = 25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Hysteresis @0V @V+
2.4 0.1 10 0.8 0.1 0.3 10
V A V A V
IOUT = -100mA IOUT = +100mA V+/GND Source/Sink Source/Sink 200
1.5 2 0.2 4.0
4 4 10
A A mA
Pull-Down Resistance Output Leakage Current Peak Output Current Continuous Output Current
POWER SUPPLY IS VS Power Supply Current Operating Voltage V = 15V, TA = 25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT Input = V+ 4.5 4.5 7.5 16 mA V
AC Electrical Specifications
PARAMETER
DESCRIPTION
SWITCHING CHARACTERISTICS (VDD = VH = 12V; VL = -3V) tR Rise Time CL = 1000pF CL = 2000pF tF Fall Time CL = 1000pF CL = 2000pF tD-ON tD-OFF Turn-On Delay Time Turn-Off Delay Time See Timing Table See Timing Table 7.5 10 10 15 18 18 20 25 25 20 ns ns ns ns ns ns
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EL7104 Timing Table
5V Input 2.5V 0 90%
Inverted Output EL7114
10%
Non-inverted Output EL7104
90%
10%
tD1
tF tR
tD2
tR tF
Standard Test Configuration
1 2
8 6
4.7F
D.U.T. Input Signal
7
Output Signal
4
5
2000pF
Simplified Schematic
3
EL7104 Typical Performance Curves
MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE
PEAK DRIVE vs SUPPLY VOLTAGE INPUT CURRENT vs VOLTAGE
QUIESCENT SUPPLY CURRENT
"ON" RESISTANCE vs SUPPLY VOLTAGE
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EL7104 Typical Performance Curves (Continued)
AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY RISE/FALL TIME vs LOAD
RISE/FALL TIME vs SUPPLY VOLTAGE
PROPAGATION DELAY vs SUPPLY VOLTAGE
RISE/FALL TIME vs TEMPERATURE
RISE/FALL TIME vs TEMPERATURE
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EL7104 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
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EL7104 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7

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